The present invention relates generally to semiconductors and more specifically to interconnect barrier materials.
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called xe2x80x9cmetallizationxe2x80x9d, and is performed using a number of different photolithographic and deposition techniques.
One metallization process, which is called the xe2x80x9cdamascenexe2x80x9d technique, starts with the placement of a first channel dielectric (oxide) layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel dielectric (oxide) layer to form the first channel openings. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel opening to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as xe2x80x9cbarrier layer herein). It should be noted that some barrier materials also have good adhesion, which is why the adhesion layer is optional. A xe2x80x9cseedxe2x80x9d layer is then deposited to act as a seed for additional conductive material to be deposited. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel dielectric (oxide) layer and damascenes the first conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metallization process, which is called the xe2x80x9cdual damascenexe2x80x9d technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel dielectric (oxide) layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric (oxide) layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel dielectric (oxide) layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel dielectric (oxide) layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop (nitride) layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and a cylindrical via opening to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metallization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as pure tantalum (Ta), titanium (Ti), or tungsten (W), is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited barrier layers to underlying doped regions and/or conductive channels. Barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN), titanium/titanium nitride (Ti/TiN), and tungsten/tungsten nitride (W/WN) have been found to be useful as adhesion/barrier material combination for copper interconnects. It will be understood that either the pure metals or the metal compounds may be used either singularly or in combination.
For capping barriers between conductive channels, the preferred barrier material has been silicon nitride since it is a good barrier material. However, it has a high dielectric constant which means it tends to increase capacitance between channels and thus reduce semiconductor circuit speed.
However, even with the various types of barrier layers, copper is still subject to strong electro-migration, or movement of copper atoms under current which can lead to voids in the copper channels and vias. Copper also has poor surface adhesion. A solution, which would form a better capping material with better surface adhesion to reduce electro-migration and a lower dielectric constant, has been long sought. As the semiconductor industry is moving from aluminum to copper and other type of materials in order to obtain higher semiconductor circuit speeds, it is becoming more pressing that a solution be found.
The present invention provides a semiconductor interconnect barrier between channels and vias as between channels and dielectrics, and a manufacturing method therefor. The material provides a lower dielectric constant, lower diffusion barrier characteristics, lower surface diffusion characteristics, and improved adhesion over conventional silicon nitride.
The present invention further provides a self-aligned semiconductor interconnect barrier between channels and vias selected from tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof. The barrier is self-aligned and formed by etching a recess in a deposited channel conductor, depositing the barrier material, and removing the barrier material outside the channel by chemical-mechanical polishing.
The present invention further provides a method of manufacturing self-aligned semiconductor interconnect barriers between channels and vias of any desired material.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.